Workshop II

1^st Workshop on Selecting Embedded Processor and Memory IPs

Organizer and Moderator:

Yervant Zorian, Virage Logic, Inc.

Summary:

Designers are facing increased market pressure to rapidly introduce new products, which shortens the time available for research and development. Many semiconductor companies – both fab and fabless – are increasingly relying on external sources or technical expertise for various components of the system-on-chip (SoC) design. The use of proven third-party semiconductor intellectual property (IP) components allows semiconductor companies to meet market pressures while continuing to focus on the portions of the SoC that constitute their core competencies. The use of third-party IP facilitates design reuse and allows for a building-block design approach. With silicon complexity increasing at more than twice the rate of design productivity, a significant “design gap” has emerged. In order to meet ever-shrinking design cycles, semiconductor and electronic systems companies are turning to IP suppliers for pre-designed, proven-in-silicon circuit elements such as microprocessors, memories, analog or mixed-signal, and general-purpose logic.  One area in which fabless companies can really take advantage of third party IP is embedded processors and memories, which is picking up momentum due to the rise of the Internet and communications. In fact, according to Semiconductor Industry Association (SIA), and as soon as next year, over half of the chip’s surface will be memory, and SOCs will contain numerous heterogeneous processors working in harmony.  In the past, system designers have generally used stand-alone or discrete memories and processors. The transition from stand-alone to embedded processors and memories is not a simple one given the availability of a wide set of third party providers. This workshop discusses the wide range of criteria for choosing embedded processor and memory cores for today’s System-on-Chip, such criteria includes interoperability, flexibility, optimization, validation, portability, retargetability, manufacturability, and certification. This Workshop provides the ideal forum to engage in informal discussion on this difficult topic. It intends to bring together system designers, IP providers, EDA tool vendors and semiconductor manufacturers where the presenters will share their experiences and demonstrate the main trade-offs in determining the right embedded processor and memory IP types for a given SOC.

Workshop Schedule:

8:30-10:15 Session II-1

Where High Density Embedded memories are needed?

Piotr Sidorowicz, ATMOS, Canada

Mike Briner, SST, USA

10:15-10:30     coffee break

10:30-12:15 Session II-2

Selecting embedded SRAM cores with High Quality and Yield

Alex Shubat, Virage Logic, Fremont, CA

Yervant Zorian, Virage Logic, Fremont, CA

12:15-1:15pm    lunch

1:15-3:00pm Session II-3

Using Optimized Processor Cores

Larry Hudepohl, MIPS Technologies, Mountain View, CA

3:00-3:15pm     coffee break

3:15-5:00pm Session II-4

Where to use configurable Processor Cores?

Kaushik Sheth, Tensilica, Santa Clara, CA  

Chung Chen , 3DSP, Irvine, CA