Plenary Session I







Bharath Rajagopalan, ISQED Conference Chair

Kenneth Shepard, ISQED Technical Program Chair







Welcome and Introduction

Best Paper Award








1P.1 Platform Leadership in the Ambient Intelligence Era


Bob Payne

US CTO and Senior Vice President/GM of System ASIC Technology, Philips Semiconductors


Design reuse has become essential to cope with the ever-increasing design complexity. IP level reuse alone has proven insufficient. Platform based design allows the validation of a robust combination of IP blocks and provides a reference HW and SW baseline which can be supported with an integrated development environment. Several years ago we transitioned into the streaming data era with most systems serving as content generation appliances, content consumption appliances or content distribution equipment. Now we have entered the age of ambient intelligence where the streaming data is served up through wireless links. What will platform leadership look like in this new era? How will the SoC infrastructure change as we move to 90nm technology with more than 30M gate per square centimeter integration capacity? How are usage patterns changing and what represents the killer application that enhances the users quality of life by enabling more advanced interaction with the ambient intelligence? What is it going to take to make a step function improvement in system level design productivity? What happens when power optimization becomes the dominant design consideration? What about SoC affordability? What will the SoC design of the future look like? These are just some of the thought provoking issues that will be addressed in Bob Payne’s keynote.      




9:15am - 9:45am

1P.2    Quality SoC Design and Implementation for Real Manufacturability



Susumu Kohyama

Corporate Senior Vice President, Toshiba Corporation


Device miniaturization near 100nm node and beyond together with extreme multi-level interconnect started to create fundamental economical and engineering challenges. Especially, past success model of “Layer Masters” confessed difficulties to fill the gaps between each separated layers to complete integrated results, for meeting performance and yield with a reasonable timing. However, it is also obvious that classic IDM model proved to be so inefficient,  since inevitable separation and standardization of various aspects of design and technology are not established adequately. Those issues are even more significant when we discuss complex SoCs for 90nm and 65nm nodes, where design and implementation commingle in various different manners. A solution for these challenges is a new open idm model where open collaboration and strong differentiator are essential.

This presentation will discuss from a “SOC Centric Open IDM” perspective, the whole flow of design and implementation for real manufacturability, where true knowledge of integration and management skill function to enhance differentiators on top of open platforms.    




9:45am - 10:15am


1P.3    Quality Challenges of the Nanometer Design Realm


Ted vucurevich

Senior Vice President and Chief Technical Office, Cadence Design Systems, Inc.


It is commonly agreed that sub-nanometer design is electronic design technology’s next big challenge. With the economic stakes higher than ever, the vendors of electronic design solutions must put themselves into their customers’ shoes through comprehensive, high-quality programs. My understanding of the differences designers face at geometries below 100 nanometers has led to my discussion of some of the challenges the industry faces in the sub-nanometer realm. This includes the domination of wires in digital design, which requires the ability to design the best quality wires through continuous convergence, a wire-centric methodology. In the nanometer world, the front-end and back-end disappear, leaving the prototype as the chip. This includes detailed wiring, and a new full-chip iteration every day. Most sub-nanometer ICs and SOCs will be digital/mixed-signal. This leads to custom design issues, such as integrating sensitive circuits with massive digital and mixed-signal design, productivity and foundry interface. Nanometer soc verification includes digital, analog and software, and a 70 percent silicon re-spin rate because of associated functional errors. At sub-nanometer levels, design-in becomes a major bottleneck, especially across a design chain, which can only be solved by silicon-package-board co-design.        




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