Session 6A

3:30pm - 5:30pm


Interconnect Parasitic Effects



Dennis Sylvester, University of Michigan

Rajendran Panda, Motorola






6A-1    On-Chip Interconnect Inductance - Friend or Foe (Invited), Simon Wong, Stanford University, Stanford, CA   



6A-2    Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact, Takashi Sato, Hiroo Masuda1, Hitachi, Ltd., Tokyo, Japan and  1Semiconductor Technology Academic Research Center, Kanagawa, Japan



6A-3    On the Accuracy of Return Path Assumption for Loop Inductance Extraction for 0.1m Technology and Beyond, SoYoung Kim, Yehia Massoud1, S. Simon Wong, Stanford University, Stanford, CA and 1Synopsys Inc., Mountain View, CA        



6A-4    Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow, Payman Zarkesh-Ha, S. Lakshminarayann, Ken Doniger, William Loh, Peter Wright, LSI Logic Corp., Milpitas, CA      



6A-5            Analyzing the Internal-Switching Induced Simultaneous Switching Noise, Li Yang, J.S. Yuan, M. Hagedorn1, University of Central Florida, Orlando, FL, 1Theseus Logic, Inc., Maitland, FL   


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