Sponsored by Advanced Packaging/Penn Well
Evening Panel Discussion
& Package Co-Design: Challenge or Dream?
Marco Casale-Rossi, STMicroelectronics
Richard Goering, EETimes
recent years, major breakthroughs have occurred in packaging technology, which
have led to the industrialization of several kinds of new packages, more
powerful, and yet more flexible, in the attempt to cope with the challenges
posed by multi-million gates and multi-GHz systems-on-a-chip (SOC). While
offering a great deal of opportunities, ball-grid array (BGA) substrates,
flip-chip and multi-stacked dies require an unprecedented level of integration
between IC and package design and verification.
integration, however, requires a change in methodology, with the availability of
new EDA tools, and a major shift in the profile of the designers and engineers
involved which, to a certain extent, have to acquire each other competences.
necessary, this cannot be given for granted. While BGA is a reality, flip-chip
is still a question mark for the majority of the applications, due to both cost
reasons and lack of commercial EDA tools. A package re-use discipline is
becoming a must to avoid a package design start for each IC design start, with
expensive substrates scraps. How to implement it? Interoperability between
Cadence and Synopsys and the rest of the EDA world is a key aspect, as customers
donít want to be further bound to few vendorsónor wants the FTC! How to
panel is not about packages nor about ICs, itís about whether todayís
electronic systems can be successfully designed and assembled in their target
package, without taking into consideration each other requirements since the
very early beginning. Itís about the requirements, the challenges and the
on-going initiatives, if any.
Camposano, CTO, Synopsys
Carlo Cognetti, VP Corp. Package Dev., STMicroelectronics
Khan, VP Design Foundry, Cadence Design Systems
Lou Scheffer, Architect, Cadence Design Systems
Symposium on Quality of Electronic Design