Tutorial Track D


Design for Reliability


Chair and moderator: Mohsen Alavi, Intel Corporation



Tutorial D1

09:00am – 10:30pm


Overview of Reliability Issues in Deep Sub-Micron Digital CMOS Technology and their Interaction with Circuit Design Considerations


Organizer and Presenter: Mohsen Alavi, Intel Corporation


During the operation of integrated circuits, electrical and thermal stress result in wear out of circuit components and degradation of key parameters and ultimately, catastrophic failure. Often times, failure of product functionality in meeting desired operating specifications occurs due to these parametric shifts and long before catastrophic failure. Therefore, circuits designed to allow larger shifts in parametric degradation result in enhanced product reliability. Such design practice requires good understanding of physical mechanisms resulting in degradation and good models to predict it’s behavior vs. stress. Furthermore, understanding of the statistics of degradation is needed to evaluate overall product failure rates.

As technology scaling reduces device dimensions and increases circuit complexity, the challenge of ensuring product reliability increases in two ways. Namely, many degradation mechanisms such as electromigration or soft error become more pronounced while tools and techniques to model degradation in more complex circuits become more challenging. Moreover, the continuous pursuit of circuit performance often results in a trade off with reliability such as the case with higher Vcc for faster products vs. dielectric reliability.

This tutorial presents an overview of various physical mechanisms resulting in device degradation and their relation to stress conditions in MOS logic technology. For each degradation mechanism, circuit impact and design consequences will also be discussed. Mechanisms will include hot carrier effects, transistor bias-temperature stability, gate dielectric wear out, plasma induced gate charging, interconnect electromigration, electro-static discharge (ESD), and soft error. Future challenges posed by technology scaling will also be discussed.




Tutorial D2

10:30am – 12:15pm

Noise Analysis for 0.13µm and Beyond


Organizer:  Ken Tseng, Cadence Design Systems

Presenters: Kishore Singhal, Agere Systems , Vinod (Narayanan) Kariat, Cadence Design System, Ken Tseng, Cadence Design Systems


At 0.13µm and beyond, ignoring signal integrity is a luxury no designer can afford; SI issues are no longer the purview of high-performance designs. Hence most designers need an awareness of Signal Integrity analysis, prevention and correction. The presenters will draw on their experiences in Signal Integrity over the last several years to present a pragmatic and practical tutorial on noise analysis, prevention and correction.

Section 1: Fundamental Principles

In this section, we will discuss the fundamental issues that give rise to noise in digital designs. This will start with the technology trends that are giving rise to an increase in noise problems. Then we cover different types of noise effects and the factors that govern them. We will also discuss the fundamental principles of noise analysis.

Section 2: Noise Analysis, Prevention and Correction

In this section, we will discuss how noise effects influence different stages of the design flow, from early prototyping to final layout, including prevention and correction techniques.

Section 3: Experience with Noise Issues in the Design Flow

In this section, we will discuss several practical considerations associated with putting noise analysis techniques into the design flow. We discuss the approaches that yield reasonable results in practice.

Section 4: Future Considerations

This section covers some of the emerging issues that we expect to surface in the future due to technological and manufacturing considerations. We will cover issues associated with Inductance, SOI, copper interconnect and various manufacturing rules.



Tutorial D3

1:30pm – 3:00pm


NBTI/HCI Modeling and Full-Chip Analysis in Design Environment


Organizer and Presenter: Lifeng Wu, Celestry


Hot-carrier (HC) degradation and negative bias temperature instability (NBTI) of MOS devices are the two most important reliability concerns for deep submicron (DSM) designs. HC degradation occurs when the channel electrons are accelerated in the high electric field near the drain of the MOS device and create interface states, electron traps, or hole traps in the gate oxide near the drain. LDD structure has become the standard drain structure to alleviate HC effects and the device-based DC criteria have been used extensively to qualify devices for HC reliability. It is becoming clear that these guidelines are too conservative for DSM technologies. It is therefore strongly desirable that circuit reliability simulation using a realistic AC (transient) circuit operation condition should be on the fingertips of the circuit designers to achieve the following goals: to maximize design performance by minimizing design guard-band, to speed up timing closure by reducing design iterations and to ensure circuit reliability by fixing design reliability problems. How to fit reliability simulation into the design environment is a more interesting topic from designer’s perspective.

  Compared to the more matured studies and solutions on HC effects, the studies on NBTI reliability has just started. NBTI reliability is becoming an increasingly important as the thickness of gate oxide film scaled down to less than 50 Angstrom, which is common for DSM designs. Unlike HC degradation which needs high electric field at the drain, NBTI effect can be significant even when the drain-source is zero biased. This implies that circuits could undergo NBTI stress even at standby operation condition! NBTI effect becomes more severe under high temperature stress. The popular burn-in procedure is being re-considered by designers to maintain acceptable yield. The recovery of NBTI effect is another important issue to reduce design margin.        

This tutorial provides an overview of the HC and NBTI effects including physics, impact on circuit performance, modeling and simulation technologies. Both full-chip transistor-level and gate-level solutions will be presented with million-transistor/gate capacity and high accuracy.        


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