Plenary Session I
Sponsored by Synopsys
Welcome and Introduction
Bharath Rajagopalan, Texas Instruments
Kaustav Banerjee, University of California, Santa Barbara
1P.1 Simplify: Enable Quality, Enable Innovation
Sr. VP and General Manager
the old sales adage goes, “Nothing happens until somebody sells something.”
For the semiconductor-based electronics industry, the never-ending challenge is
to find and sell the next IC-based new “something” (or “somethings”)
that consumers just can’t live without. It’s an immense and extremely
expensive undertaking to find/create/deliver a killer app, requiring a
single-minded, undistracted business focus and an immense amount of creative
design innovation. Fortunately, there is a wealth of business-savvy, creative
systems companies able to meet that challenge, as long as they are free to
concentrate on what drives their core competency: designing and selling exciting
new business systems and consumer devices. What they need from their chip
manufacturers is an agreement on specs, models, pricing, and delivery. Simple.
Fortunately, there are semiconductor firms up to the challenge, as long as they
are free to exercise their core mission: designing and selling faster and
slicker chips, often now with software and boards attached. They need to focus
on taking their customer’s performance specifications and turning out a system
on a chip that does exactly those things, on time and on budget. What they need
from their EDA vendors are tightly integrated design tools that allow them to
meet their goals of performance, price, and predictability. Simple.
Unfortunately, these industries don’t reflect this simplified, rosy picture… yet. The hard reality is, however, that they do have to get there, and soon, or live with dwindling prospects for the future. This presentation will discuss strategies for simplifying the semiconductor value chain, thereby enabling each segment to focus on doing well what it does best, for the sake of the future of the entire electronics industry.
9:15am - 9:45am
1P.2 Design for Manufacturing? Design for Yield!!!
Vice President and General Manager
Cadence Design Systems, Inc.
Today’s nanometer-scale designs are two orders-of-magnitude more complex than designs were in the early 1990s and are commonly manufactured with processes at or below the 130nm feature size. This has brought about a fundamental change in the way design teams must approach the release for their design data to their manufacturing partners. In the past, once a design was taped out and proven to be functional, the responsibility for ramping yield and enhancing the profitability of a design was primarily the responsibility of the manufacturing partner. This is no longer possible at 130nm and below. Once a manufacturing process has stabilized, direct action must be taken by each and every design team to "tune" their design for yield. Design-specific yield enhancement is the new frontier in EDA and while it includes the traditional Design for Manufacturing (DFM) technologies, it also covers much more. Failure to consider yield-degrading effects in IR drop, signal integrity, electro migration, and process variation will result is severe downstream problems in timing closure, functional errors during system bring-up, and the inability to achieve silicon yield and quality targets. In this talk Marc Levitt will discuss what is needed in a new generation design-for-yield tool suite to address the quality of silicon at its source.
- 10:15am 1P.3
Nanotechnology-Nanoscale Molecular Memory
9:45am - 10:15am
1P.3 Nanotechnology-Nanoscale Molecular Memory
Shih-Yuan (SY) Wang
Senior Scientist Quantum Science Research
Hewlett Packard Laboratories
An overview of nanotechnology research at HP Labs/ Quantum Science Research
will be given with focus on nanoscale molecular memories. Densities of 100 Gb/cm2
are within reach. QSR aim is to break away from the current “scaling” down
approach and look for and/or invent innovative approaches that have the
potential for high volume manufacturability to break through the ITRS Red Brick
Wall and push the limit of the technology. Nanofabrication challenges and
possible applications will also be discussed.
An overview of nanotechnology research at HP Labs/ Quantum Science Research will be given with focus on nanoscale molecular memories. Densities of 100 Gb/cm2 are within reach. QSR aim is to break away from the current “scaling” down approach and look for and/or invent innovative approaches that have the potential for high volume manufacturability to break through the ITRS Red Brick Wall and push the limit of the technology. Nanofabrication challenges and possible applications will also be discussed.
for Quality Electronic Design (ISQED Org.)