Session 5C

San Martin Room

10:30am - 12:00pm

Variability Issues in Nanoscale Circuits

Chairs:    Sharad Saxena, PDF Solutions

Nikos Konofaos, University of Patras, Greece

10:30am

Introduction

10:35am

5C.1       

Modeling Intrinsic Fluctuations in Decananometer MOS Devices due to Gate Line Edge Roughness (LER)

Norman Gunther*, Emad Hamadeh**, Darrell Niemann*, Iliya Pesic***, Mahmud Rahman*, * Santa Clara University, ** Applied Micro Circuits Corp., *** Silvaco

11:05am

5C.2       

Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization

Paul Friedberg, Yu Cao, Jason Cain, Ruth Wang, Jan Rabaey, Costas Spanos, University of California at Berkeley

11:35am

5C.3       

Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations

Vishak Venkatraman, Wayne Burleson, University of Massachusetts Amherst