Monday March 27, 2006
TUTORIAL I I
Variability and Its Impact on Design
Anirudh Devgan, Magma Design Automation
Keith Bowman, Intel Corporation
Michael Orshansky, University of Texas-Austin
Sachin S. Sapatnekar, University of Minnesota
As digital designs scale down into the sub-100nm regime, the effects of variations are seen to dramatically affect the behavior of the circuit. These may arise from:
1. Fluctuations attributed to the manufacturing process (e.g., drifts in channel length, oxide thickness, threshold voltage, or doping concentration), which affect the circuit yield.
2. Variations in the environmental operating conditions (e.g., supply voltage, temperature, or particle strikes that lead to soft errors) after the circuit is manufactured, which affect the correctness of the behavior of the design.
These variations have been observed at the 90nm technology node, and trends show that this will be even more significant from the 65nm node onwards. Some of these variations are entirely deterministic (metal fill density, etc.), while others are random, as their cause is either unknown, unattributable, or too difficult to model. Either way, it is imperative to analyze their effects and design circuits to be tolerant to variations. Circuit performance, in terms of both timing and power, is shown to vary significantly under process and environmental variations. While timing can vary by unacceptably large amounts, a second important factor is the leakage power (which is becoming a major fraction of the total power): its exponential dependence on process parameters can lead to large swings in the power dissipation from die to die after manufacturing. Therefore, variation-tolerant design is imperative for the design of next-generation digital integrated circuits. Traditional circuit design techniques tackle this by using several design corners, but they are insufficient under the magnitude and scale of these variations for several reasons: first, they are incapable of accurately predicting parametric yield, and second, they lead to the run-time explosion due to the increasing number of corner cases that need to be considered. While variation-tolerant design has been practice in the analog world for many years, the scale of digital problems, where circuits may have a billion transistors or more, renders those techniques inadequate.
The past few years have seen a great deal of work on robust design techniques for digital circuits, ranging from employing statistical methods for analysis and optimization at the design phase, to building in compensatory techniques to recover performance (timing and power) after the circuit is manufactured. The objective of this tutorial is to present an overview of the state of the art in variation-tolerant design, while highlighting important unsolved research problems for the future. The tutorial will consist of the following segments:
Sources of variation A good understanding of the sources and nature of process variation is key to accurately simulating their impact design. As the need for better modeling of variation margins arises, so does the need to understand and model the systematic sources of variation and incorporate them in the design flow. This portion of the tutorial will introduce the various sources of variation, focusing on their impact on design and how to mitigate their effects. Design techniques to overcome variations: The impact of process, voltage and temperature (PVT) variations on performance and power, and on circuit robustness will be discussed. Scaling trends of these variations and their impacts will be presented. Promising design and circuit techniques that can mitigate variation impacts and make designs variation-tolerant will be described. Furthermore, models and measurement methodologies of key systematic and random process-related variations, needed to enable robust designs, will be presented.
Design techniques to overcome deterministic variations In this segment, we will address the techniques for dealing with systematic sources of variability. These work by identifying the physical mechanism responsible for a particular pattern of variation, and then compensating for it. We will cover the use of optical proximity correction (OPC), phase-shift masking (PSM), and sub-resolution assist bars to improve depth-of-focus and feature resolution in photolithography, and the use of tiling (dummy wire insertion) for greater metal layer planarity. Design techniques to overcome random variations: In the last section of the tutorial we will discuss analysis and optimization strategies for design in the presence of variability. We will cover the recent work in statistical static timing analysis (SSTA), and discuss the algorithmic approaches to efficient SSTA, including block-based algorithms suitable for incremental analysis and useful within the optimization loops, as well as the sign-off quality path-based algorithms. We will then cover the growing body of work on the fully statistical optimization methods, which optimize the performance of a digital circuit under random variations, using techniques such as transistor and gate sizing, and statistical dual-Vth optimization, and promising significant advantages in terms of timing and leakage power parametric yields.
International Society for
Quality Electronic Design (ISQED Org.)