InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization

Kai-hui Chang,  David Papa,  Igor Markov,  Valeria Bertacco
University of Michigan at Ann Arbor


The explosive increase in design complexity and advances in IC manufacturing technology affect all aspects of the final circuit's performance and functional correctness. As interconnect becomes the dominating factor in delay and power at the latest technology nodes, tremendous efforts are dedicated to physical synthesis optimizations, posing even greater challenges in validating the correctness of such optimizations. Common design methodology delays the verification of physical synthesis transformations until the completion of the design phase. This approach breaks down at current complexity levels because it makes the isolation of errors extremely difficult. In addition, the lack of interoperability between verification and debugging tools greatly limits engineers' productivity. Since functional correctness is a vital design quality, enormous efforts have been devoted to verification and debugging, which can otherwise be used to improve other quality aspects. To address these problems, we propose a fast incremental verification system for physical synthesis optimizations, InVerS, that provides error detection, diagnosis, and visualization capabilities. This system allows engineers to discover errors earlier and fix them more easily -- thus reducing the burden on the verification task and enabling the application of more aggressive optimizations to improve other performance aspects of a design.