Comparative Robustness of CML Phase Detectors for Clock And Data Recovery Circuits

David Rennie and Manoj Sachdev
University of Waterloo


This paper presents an analysis of the robustness of CML based phase detectors with respect to the scaling of CMOS processes. Phase detectors are an important part of CDR circuits, which in turn are an integral part of wireline serial data communication systems. Serial data communication circuits are increasingly being integrated into monolithic CMOS ICs, hence their robustness is of critical importance. Three phase detectors are analyzed over corners in three standard CMOS processes: 180nm, 130nm and 90nm. The results of the simulations show that the total variation of the static phase offset increases with scaling for all phase detectors. The presence of static phase offsets is shown to have a negative impact on the BER of a CDR circuit. The analysis shows that the DFF binary phase detector has significant advantage in terms of robustness however it also has performance limitations. Both the Alexander and Hogge phase detector experience significant and increasing variations in static phase offset as the technology scales.