An Automated and Fast OPC Algorithm for OPC-aware Layout Design

Ye Chen,  Zheng Shi,  Xiaolang Yan
Institute of VLSI Design, Zhejiang University


To reduce design spin time, OPC-unfriendly patterns in the layout should be found out by the designer before the layout sent to the manufacturer. It can be done by first run a ``trial OPC'' step on the layout, then run a ORC step to verify the OPCed layout. In this paper we introduce a new OPC algorithm which can automatically extract simple OPC recipes from OPCed layouts. It also has a correction speed of about 20 times faster than a standard model based OPC algorithm. The convenient usage and fast speed make it an appropriate algorithm for designers to do a ``trial OPC''.