An MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation

Takashi Sato,  Takumi Uezono,  Shiho Hagiwara,  Kenichi Okada,  Shuhei Amakawa,  Noriaki Nakayama,  Kazuya Masu
Tokyo Institute of Technology


A MOS transistor-array structure and an accurate measurement procedure of subthreshold leakage current variation is proposed. New contributions consist of two architectural improvements called LCS and PES, and measured data treatment called MCC. The LCS, leakage current cut-off switch, reduces unwanted leakage current of the non-target devices which masks the target leakage current. The PES, potential equalizing supply, further reduces masking current to an atto ampere order by setting source and drain terminals of the LCS equal. The MCC, masking current cancellation, improves measurement accuracy by subtracting remaining masking current. The proposed array structure and the procedure virtually eliminate usual constraint on the number of transistors that can be present in an array. The array structure also offers greater flexibility in choosing a row-column aspect ratio and allows different types of MOS transistor to be interweaved. Simulation study proved effectiveness of the proposed architecture showing well over a million of devices to be measurable with less than 1 \% error.