Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis

Marc Boule,  Jean-Samuel Chenard,  Zeljko Zilic
McGill University


Assertion Based Design, and more specifically, Assertion Based Verification (ABV) is quickly gaining wide acceptance in the design community. Assertions are mainly targeted at functional verification during the design and verification phases. In this paper, we concentrate on the use of assertions in post-fabrication silicon debug. We develop tools that efficiently generate the checkers from assertions, for their inclusion in the debug phase. We also detail how a checker generator can be used as a means of circuit design for certain portions of built-in self test circuitry, and more generally the design of monitoring circuits. Optimal subset partitioning of checkers for a dedicated fixed-size reprogrammable logic area is developed for the efficient use of dedicated debug hardware.