A Power Network Synthesis Method for Industrial Power Gating Designs

Kaijian Shi,  Zhian Lin,  Yi-Min Jiang


A sleep transistor P/G network synthesis method has been developed to address the requirements from industrial power-gating designs, where sleep transistors are custom designed with a fixed size and the optimal sleep transistor P/G network is achieved by simultaneously optimizing sleep transistor insertion and placement as well as the power network grids and wires for minimum area, maximum routeabillity with a given IR-drop target.