Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations

Mosin Mondal1,  Tamer Ragheb1,  Xiang Wu2,  Adnan Aziz3,  Yehia Massoud1
1Rice University, 2AMD, 3University of Texas


A Network-on-Chip (NoC) replaces on-chip communication implemented by point-to-point interconnects in a multi-core environment by a set of shared interconnects connected to programmable crosspoints. Since an NoC may provide a number of paths between a given source and destination, a manufacturing or runtime fault on one interconnect does not necessarily render the chip useless. It is in part because of this fault tolerance that NoCs have emerged as a viable solution for implementing communication between functional units on a chip in the nanometer technology process nodes, which have a very high defect rate. In this paper, we quantify the the fault tolerance offered by an NoC. Specifically, we develop an analytical model for the probability of failure in buffered global NoC links due to interconnect resistance variation caused by dishing, and effective channel length variation. Using the developed probability model, we study the impact of link failure on the number of cycles required to establish communications in NoC applications.