Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm

S Ramsundar1,  Ahmad Al-Yamani2,  Dhiraj Pradhan3
1IIT, Guwahati, 2KFUPM, 3University of Bristol


Lithography based IC fabrication is rapidly approaching its limit in terms of feature size. The current alternative is nanotechnology based fabrication, which relies on self-assembly of nanotubes or nanowires. Such a process is subject to a high defect rate, which can be tolerated using carefully crafted defect tolerance techniques. This paper presents an algorithm for reconfiguration-based defect tolerance in nanotechnology switches. The algorithm offers an average switch density improvement of 50% to 100% to most recently published techniques.