Analytical modeling of hot-carrier induced degradation of MOS transistors for analog design for reliability

Benoit Dubois,  Jean-Baptiste Kammerer,  Luc Hébrard,  Francis Braun
Institut d'Electronique du Solide et des Systèmes


An CMOS transistor ageing compact model is presented and the procedure that allows to extract its parameters is proposed in this paper. By using a simple example, we show how such a model can be used to forecast the drifts of the main characteristics of a CMOS circuit. The more, we demonstrate that this model can also be used to help the designer to choose and/or modify a circuit in order to minimize the hot-carrier induced degradations. Simulation results compared to the analytical study are also shown.