Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS

Rajani Kuchipudi and Hamid Mahmoodi
San Francisco State University


Straining of silicon improves mobility of carriers resulting in speed enhancement for transistors in CMOS technology. Traditionally, silicon straining is applied in a similar ad-hoc manner to the whole die including logic and memory. Speed enhancement achieved for both NMOS and PMOS devices is desirable in logic circuits for performance enhancement because both PMOS and NMOS devices lie in critical delay paths. In SRAM cells however, PMOS devices are not in the delay path and hence made small to minimize cell area and improve the write stability of the cell. Hence, speed enhancement of PMOS does not result in any reduction in cell access time and in fact it degrades the cell write ability. Hence, optimal method and amount of silicon straining for logic and memory should be different. In this paper, we propose an optimal straining solution for both logic and memory. Based on simulation results in a predictive 45nm process technology, the proposed straining solution enhances circuit performance by 15.6% in SRAM and 39.3% in Logic while satisfying stability requirements. We also propose a co-design optimization methodology that allows optimizing circuit parameters (such as transistor sizing and supply voltage) and process parameters (in this case amount of silicon straining) at the same time for both low power and high performance targets. We found that co-design of supply voltage and silicon straining is very helpful for both low power and high performance targets, whereas co-design of sizing and silicon straining dose not provide any considerable improvements. Our results show that by co-design of supply voltage and silicon straining, power reduction of 38% and 49% is achieved in SRAM and logic, respectively. We also expanded our co-design approach for joint optimization of various circuit and device parameters such as supply voltage, straining, and threshold voltage. The results show that the co-design can reduce leakage by 80% and improve performance by 50%. The developed optimization methodology thus provides a device and circuit co-design framework which is essential as the technology continues to scale to nano-scale regimes.