SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-based FPGAs

Hamid Zarandi1,  Seyed Ghassem Miremadi2,  Dhiraj K. Pradhan1,  Jimson Mathew1
1University of Bristol, 2Shrif University of Technology


In this paper, we propose a new SEU-mitigative placement and routing of circuits in the FPGAs which is based on the popular VPR tool. The VPR tool is modified so that during placement and routing, decisions are taken with awareness of SEU-mitigation. Moreover, no redundancies during the placement and routing are used but the algorithms are based on the SEU avoidance. Using the modified tool, i.e., S-VPR, the role of placement and routing algorithms on the fault-tolerance of circuits implemented on FPGAs is achieved. The secondary propose of this paper is to find which of placement or routing is more suited for decreasing SEU sensibility of circuits and to find whether these SEU sensibility reductions are cumulative or not when they applied in sequence. We have investigated the effect of S-VPR on several MCNC benchmarks and the results of the placement and routing have been compared to the traditional one. The evaluations of results show that placement and routing can decrease the SEU rate of circuits implemented on FPGAs about 18% and 12%, respectively. However, it increases critical path delay and power consumptions of the circuits up to 5% and 8%, respectively. This means that without any redundancies, just by means of fault-avoidance method, mitigation of SEU effects would decrease up to 22% significantly and this method is notable compared to previous TMR and DWC mechanisms.