OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts

Tetsuya Iizuka,  Makoto Ikeda,  Kunihiro Asada
University of Tokyo, JAPAN


As the VLSI technologies scale down to the subwavelength lithographic regime, resolution enhancement techniques such as Optical Proximity Correction (OPC) become essential to realize the fine patterning. This paper proposes an OPC-friendly de-compaction method for standard cell layouts to reduce the mask cost. The proposed de-compaction method expands the spacings between the polygons inside the layout and eases the optical proximity effects under given timing constraints using Linear Programming. With the timing constraints, we can minimize the optical proximity effects by modifying non-timing-critical patterns. The layout after de-compaction can be printed correctly even by the modest OPC. Therefore, we can generate the OPC-friendly cell layouts and can reduce the OPC data volume using the proposed method. We use the fractured data size during mask creation to evaluate the OPC cost. Experimental results show that the proposed method effectively reduces the mask data size by de-compacting the layout and the reduction ratio is expected to be larger in the future technology. Using the proposed method, the maximum 18.4% reduction in mask data size is achieved for cell layouts in 65nm technology.