Cross Layer Error Exploitation for Aggressive Voltage Scaling

Amin Khajeh Djahromi1,  Ahmed Eltawil1,  Fadi Kurdahi1,  Rouwaida Kanj2
1University of California, Irvine, 2IBM Austin Research Labs


This paper shows that by co-designing circuits and systems, considerable power savings are possible if the inherent data redundancy of candidate systems such as wireless is used to compensate for hardware failures. A comprehensive study of 6T SRAM failure modes is presented. The generated statistics are used to quantify a power savings of up to 28.6% for a case study of a 32 nm CMOS 3GPP WCDMA modem.