Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy

Uthman Alsaiari and Resve Saleh
University of British Columbia


As the number of transistors on a chip begins to exceed 1 billion, it will be mandatory to use a portion of the transistors for the purposes of Built-in-Self-Test (BIST) and Built-in-Self-Repair (BISR) as part of the supporting circuitry. However, this will require the use of structured logic, such as programmable logic arrays (PLAs) or structured ASIC. In this paper, we select the fastest and lowest energy PLA design to date and combine it with a block duplication strategy to construct a BIST/BISR PLA in order to establish a reference design. Then, we introduce a PLA redundancy in the form of spare columns and carry out a yield analysis. The results of the yield analysis suggest that using duplication for BIST/BISR is better suited for small PLAs while using spares is more suitable for larger PLAs. The spares needed are determined by several factors including target yield, area, power and delay.