FinFET Based SRAM Design for Low Standby Power Applications

Tamer Cakici,  Keejong Kim,  Kaushik Roy
Purdue University


It is well known that leakage savings using transistor stacks is not effective in double-gate technologies such as FinFETs (back and front-gate connected together), due to the absence of body effect. However, transistor stacking along with independent gate operation of FinFETs can offer larger leakage savings compared to that of bulk devices. In this paper, we show that the sleep transistor based source biasing technique can be an effective means to control leakage for Static Random Access Memory (SRAM) with Independent Gate FinFETs. The array area penalty of the approach is ~5%. We show that lower gate leakage at a given Short Channel Effect (SCE), lower Band-to-Band tunneling and higher sub-threshold slope offered by well tempered undoped ultra thin body FinFETs can lead to ultra low power SRAM arrays.