Parameter-Variation-Aware Analysis for Noise Robustness

Mosin Mondal,  Kartik Mohanram,  Yehia Massoud
Rice University


Increasing noise susceptibility of CMOS gates with technology scaling has been a source of major concern for the current and future technology nodes. Process and environmental variations pose additional problems by their significant impact on the performance of deep submicron designs. In this paper, we demonstrate that parameter variations can appreciably change the noise robustness of a design leading to less reliable circuit operations. We present an analytical method for efficient analysis and prediction of the noise susceptibility of CMOS gates due to design and process parameter variations. Results show that our method can accurately predict the noise susceptibility for different values of the design and process parameters that will enable design-for-noise-robustness.