Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization

Kumar Yelamarthi and Henry Chen


Due to the increased importance of speed on microprocessor circuits, the complexity in transistor sizing for timing optimization increases due to channel-connected transistors on various paths of the design. In this paper we present an efficient approach to transistor sizing of dynamic CMOS circuits for timing optimization while considering the load balance of multiple paths. The iterative optimization algorithm is a deterministic approach and illustrated first by a 2-b weighted binary-to-thermometric converter (BTC), of which the critical path is optimized from an initial delay of 287.57 ps to an optimal delay of 161.37 ps which accounts for a 43.9% delay improvement, and then by a 64-b adder portioned to a mixed dynamic-static style, of which the critical path is optimized to 686.11 ps and the power delay product is optimized to 91.6 fJ.