On-Line Adjustable Buffering for Runtime Power Reduction

Andrew Kahng1,  Sherief Reda2,  Puneet Sharma1
1University of California, San Diego, 2Brown University


We present a novel technique to exploit the power-performance tradeoff. The technique can be used stand-alone or in conjunction with dynamic voltage scaling, the mainstream technique to exploit the tradeoff. Physical design, specifically repeater insertion and sizing, is naturally signed-off at the highest performance mode. We observe that through simple modifications to the repeaters (buffers and inverters), it is possible to dynamically customize the repeater driving capacity of the design. This customization opens the door to a novel opportunity for on-line power-performance tradeoff: customizable repeaters can trade away performance for reductions in power, or vice versa. We describe a simple customization of repeaters to have an additional adjustable low-power operation mode besides their regular operational mode. Using selective logic remapping, we demonstrate how to use the new customized repeaters in a design flow that does not impact the high-performance signoff, yet attains considerable power reductions in low-performance mode. With industrial tools and real-world benchmarks at the 90nm node, we observe an average of 8.34% reduction in total system power in lower performance modes, while ensuring no sacrifice to high-performance modes. We estimate the overhead of our approach to be a tolerable 2.89% in the total device area and 3.41% in the total routing requirements, which is likely easily accommodated in the whitespace of a design.