On-chip Inductance in X Architecture Enabled Designs

Santosh Shah,  Arani Sinha,  Li Song,  Narain D. Arora
Cadence Design Systems


The inductance effects become significant for sub-100nm process designs due to increasing interconnect lengths, lower interconnect resistance values and fast signal transition times. The accurate modeling of inductance behavior is thus essential for high speed VLSI designs. Recently X Architecture has been introduced to reduce overall IC interconnect length by using diagonal wirings pervasively, resulting in smaller die sizes and higher performance. Although the resistance and capacitance of diagonal wires and their modeling are well understood, the characterization and modeling studies of diagonal wire inductance remain scarce. In this paper, we study the inductance effects of diagonal wiring, specifically inductance with return loop through diagonal (X Architecture) and Manhattan power grids. Both self and mutual inductance of Manhattan and diagonal wirings in the presence of various power grids are obtained using both FastHenry simulations and on-chip measurements. Results show that both self and mutual inductance values of diagonal signal line(s) are invariant with respect to their placement relative to the power grid. We observe that measurements done on an actual test chip agree fairly well with simulation data. This makes inductance modeling in X Architecture designs easier compared to Manhattan design, and X Architecture design has an advantage over Manhattan design from inductance perspective.