Clock distribution networks play a key role in determining overall system performance. In this paper, we investigate the effect of parameter variations on the performance of a commonly used clock distribution structure, a H-tree clock network. The design of robust high performance clock networks face significant challenges due to increasing parameter variations in sub-65nm technologies. As shown in the results, the contribution of interconnect variations to clock skew has risen by upto 3 times from 180nm to 45nm technology. It also suggests that the effect of variability is most prominent at the second and third stages of the 5-stage H-tree clock network. This analysis will help develop mitigation techniques that focus on addressing specific failure mechanisms caused by variability in clock networks.