Reducing EPL Alignment Errors for Large VLSI Layouts

Yokesh Kumar and Prosenjit Gupta
International Inst. of Information Tech., Hyderabad, India


A leading candidate for next generation lithography at sub-micron levels is electron projection lithography (EPL). EPL uses very thin membranes on which layout features are placed. To provide rigidity to this thin membrane, support structures called struts are built into membrane which divide the membrane and layout into uniform sub-fields. These sub-fields must be stitched back together on the wafer by EPL process. Alignments errors are possible during the stitching back stage. To minimize these stitching errors, minimum number of layout features must be cut while partitioning the layout into sub-fields. This problem was identified and formulated by Tang et al. in ICCAD 2002. However, all the proposed algorithms take $O(N^2)$ time and space in the worst case where $N$ is the size of input. In this paper we present an improved $O(N\log N)$ solution to the mask layout partitioning for EPL process. The algorithm presented is found to be very fast on experimental data.