Self-timed Regenerators for High-speed and Low-power Interconnect

Jae-sun Seo,  Prashant Singh,  Dennis Sylvester,  David Blaauw
Univ. of Michigan, Ann Arbor


In this paper, we propose a new circuit technique called self-timed regenerator (STR) to improve both speed and power for on-chip global interconnects. The proposed circuits are placed along global interconnect to compensate the loss in resistive wires and to amplify the effect of inductance in the wires to enable transmission line like behavior. For different wire widths, the number of STR and sizing of the transistors are optimized to accelerate the signal propagation while consuming minimum power. In 90nm CMOS technology, STR designs achieved a delay improvement of 14% over the conventional repeater design. Furthermore, 20% power reduction is achieved for the iso-delay, and 8% delay improvement for the iso-power compared with the repeater design.