Systematic Design of a Flash ADC for UWB Applications

Liang Rong,  E. Martin I. Gustafsson,  Ana Rusu,  Mohammed Ismail
Royal Institute of Technology, Sweden


This paper presents the systematic design of a 5-bit, 1.2 GSPS interpolative flash ADC for multiband OFDM UWB applications. The proposed ADC architecture employs the proven capacitive interpolation, which greatly reduce power consumption, by eliminating the need for a power hungry resistive ladder. The proposed flash ADC has been implemented in a 0.18 um CMOS process. Circuit level simulations show that the proposed architecture can achieve an SNDR of 25.3 dB, and an SFDR of 29.3 dB, with an input signal frequency of 330 MHz, when sampling with 1.2 GSPS. The ADC core dissipates 130 mW from a 1.8 V supply.