Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals

Ling Zhang1,  Hongyu Chen2,  Bo Yao3,  Kevin Hamilton4,  Chung-Kuan Cheng1
1UCSD, 2Synopsys Inc., 3Mentor Graphics Inc., 4Qualcomm Inc.


As semiconductor process technologies shrink, interconnect planning presents ever-greater challenges to designers. In this paper, we analyze, evaluate and compare various metrics with optimized wire configurations in the contexts of different design criteria: delay minimization, delay-power minimization and delay2-power minimization. We show how various design criteria influence interconnect performance and we have several observations: (1) the optimal inverter to wire capacitance ratio depends only on the technology and design goal, not on wire pitch, (2) at min-pitch, the width pitch ratios of wire for different objective functions are different: the ratio is 0.52 for minimizing delay, 0.31 for minimizing delay2-power product and 0.21 for minimizing delay-power product, (3) we derive the quantitative delay-energy trade-offs for the three objective functions: the delay-power product reduces power by 67% with a cost of 40% larger delay, while the delay2-power product reduces power by 50% with a cost of 10% larger delay, which implies that delay2-power product results a decent power saving with little cost on speed and (4) We derive the quantitative results of the impact of wire pitch on wire performance. Particularly at 70nm technology node, for bandwidth, the optimal pitch is at min-pitch, while for power, the optimal pitch is 2.35x the min-pitch, and for bandwidth over power, the optimal pitch is 1.76x min-pitch.