Compact Modeling of a PD SOI MESFET for Wide Temperature Designs

Asha Balijepalli,  Joseph Ervin,  Yu Cao,  Trevor Thornton
Arizona State University


A compact model for the partially-depleted (PD) silicon-on-insulator (SOI) Metal Semiconductor Field Effect Transistor (MESFET) is presented. The absence of a gate-oxide makes the SOI MESFET extremely robust, able to withstand high voltages, and useful for extreme environment electronics. The device has been fabricated using a standard CMOS process. In contrast to SOI MOSFETs and GaAs MESFETs, the source-substrate voltage has a significant impact on the channel current. In this work a model has been developed that includes the effect of the buried-oxide on the performance of the MESFET. The model has been verified for a wide temperature range of -180 C to 150 C. A behavioral model has been included to model the breakdown voltage. The core DC and RF models have been adapted from the commercially available Triquint’s Own Model (TOM3) MESFET model. A measurement-based approach is used to develop a 4-terminal device model. The charge-based approach, using S-parameter measurements was used to develop the capacitance model. We also propose a wide-temperature compensation technique by source-voltage modulation. This method will be more effective than traditional techniques due to a significant sensitivity of the SOI MESFET to source-substrate voltage tuning.