We propose selective scaling of device footprint for 65 nm and beyond CMOS technologies. The benefits of selective scaling of device footprint are illustrated using an ultra-thin body (UTB) fully-depleted SOI (FD-SOI) transistor as an example. We study the effect of footprint scaling on device, circuit, and system level performance. A complete 2-D device structure including both the gate region and source/drain contact regions for UTB FD-SOI FET is modeled for the numerical analysis. The results predict that an optimal footprint design can provide 45% smaller device layout area, 10% faster speed in device and simple circuit level, as well as 30% smaller chip layout area, 20% faster speed and 10% less dynamic power on overall chip performance benchmarked with a fully custom designed 53-bit pipelined multiplier.