Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes

Avijit Dutta1 and Abhijit Jas2
1Mentor Graphics, 2Intel Corp


Concurrent error detection and correction mechanisms can be efficiently incorporated in memories due to their regular structure, however logic circuits present a much greater challenge because of their irregular structure. One approach to handle the problems arising due to soft errors is to detect the errors using a concurrent error detection (CED) circuitry that monitors the circuit output for the occurrence of an error. While operating in an environment with high soft error rate and for systems with a stringent reliability and availability requirement, error detection alone may not be sufficient. While triple modular redundancy (TMR) can mask all single faults, the overhead can be unacceptably high. This paper presents a low-overhead non-intrusive technique to detect and correct the most likely soft errors using customized ad-hoc error detecting and correcting (EDAC) codes. Employing the proposed EDAC scheme can dramatically reduce the failure rate and hence increase the mean time to failure (MTTF) for logic circuits with low overhead. The proposed technique can be very useful or certain applications such as network servers, query servers, etc., which require high availability and low cost. The linearity property of the codes allows for efficient synthesis of the parity prediction logic.