a knowledge-based tool for generating and verifying hardware-ready embedded memory models

Paul Cheng
Cadence Design Systems


Using memory models in a hardware-assisted acceleration/emulation environment, as contrasted with a software simulation environment, is often infused with some very specific problems:

Behavior memory models provided by popular library vendors such as IBM, Artisan and Virage, are often unusable directly in hardware-assisted acceleration/emulation because of different types of non-synthesizable behavioral constructs, such as timing checks, loops, PLI calls, etc.

Some vendor models can also encompass extra gates for timing and functional purposes; these gates should be pruned to improve capacity in a hardware-assisted acceleration/emulation environment.

All non-RTL library cells and memory models must be mapped, and if mapping is done incorrectly, debugging can be difficult. Mapping library cells and memory models is time-consuming and can often be the significant factor in bring-up. In competitive customer evaluations, reducing this time is critical.

How to verify the memory models generated is functionally equivalent to the original behavior model.

This article describes a methodology that specifically addresses these issues.