Recently VLSI IC design has been significantly concerned with the high temperature non-uniformity in high power chips. Non-uniformly elevated temperature limits both the performance and the reliability of packaged chips. Thus far, thermal simulations have been limited to steady-state worst case conditions, which has caused the use of conservative margins in thermal designs. The temperature non-uniformity evolves with time and so do the hot spots. These transient characteristics were not simulated in prior art chip-level simulations due to the high computational expense. To drastically reduce the time for the chip-level thermal simulation, we have developed a matrix convolution technique, called the Power Blurring (PB) method. Our method renders the temperature profile of a packaged IC with maximum error less than 3% for all case studies done and reduces the computation time by a factor of 100, compared to the simulations done by the industry standard tool, ANSYS.