Design complexity is ever increasing with multi-mode, statistical timing analysis, multi-vt/VDD low power and multi-core performance based type of designs. IEEE 1800 System Verilog is a natural smooth transition language to Verilog for system level design and verification. Verilog RTL has been popularly used for many design tape outs. System Verilog (SV) extensive support exists in verification tools viz. simulators, formal for various powerful SV specific design constructs. It is envisaged that SV will be used for design tape outs soon as many design houses started using SV specific RTL constructs for system designs involving high levels of design data abstractions for various design application keeping in view of verification support. This paper analyzes on various SV design specific constructs for design Quality of Results (QOR) improvement. The specific constructs discussed for design QOR improvements are
1) Operator overloading using user defined types to bring in efficient implementation of data path operators like multiplier, adder, shift,.. 2) Parameterized module interface for different sized datapath, memory, fifo, register files.. 3) Configuration to bind a particular efficient architecture to a module based on QOR requirement 4) System level modules interface and arbitration using "interface" construct. 5) Multiple clock domain definition and interface. 6) IEEE1801 UPF low power design intent flow.