This paper presents a novel DFM (design for manufacture)-driven detailed routing algorithm that seeks to minimize the thickness range of the chip surface after copper damascene process. Based on an ECP (electroplating) & CMP (Chemical Mechanical Polishing) model, predictors for the final thickness range are abstracted and inserted into the maze routing process which is a W-shape multilevel full-chip routing framework using Depth First Search and Branch and Bound techniques in maze backtracking.
Experimental results show that compared to MR(maze routing algorithm which does not consider CMP), the improvements in the average metal density standard and the average amount of dummy fill are 14.6% and 0.96% respectively. Compared to DMR (routing algorithm which considers only CMP but does not consider ECP), the improvements in the average metal density standard and the average amount of dummy fill are 6.99% and 0.72% respectively. So the proposed algorithm can obtain improvement in optimizing CMP while the wire length and vias are not increased clearly and the completion rate is guaranteed. Therefore the yield of chips is improved.