Output Remapping Technique for Soft-Error Rate Reduction in Critical Path

Qian Ding,  Yu Wang,  Hui Wang,  Rong Luo,  Huazhong Yang
Tsinghua University, Beijing


As technology scales, soft errors in deep submicron circuits become a major reliability concern due to smaller node capacitances and lower supply voltages. It is expected that the soft error rate (SER) of combinational logic will increase significantly. Previous solutions to mitigate soft errors in combinational logic suffer from delay penalty or area/power overhead. In this paper, we proposed an output remapping technique to reduce SER of critical paths. Experimental results show up to about 20X increase in Qcritical. Due to the exponential relationship between SER and Qcritical, the SER is reduced significantly. This method does not introduce any delay penalty. The area/power overhead is limited as well. The output remapping method is based on our novel glitch width model. The analysis shows that the width of the particle strike induced glitch scales down with technology scaling, which guarantees that output remapping technique works well along with technology scaling.