Analytical Model for the Propagation Delay of Through Silicon Vias

DiaaEldin Khalil1,  Yehea Ismail1,  Muhammad Khellah2,  Tanay Karnik2,  Vivek De2
1EECS Department, Northwestern University, 2Circuits Research Lab, Intel Corporation


This paper explores the modeling of the propagation delay of through silicon vias (TSVs) in 3D integrated circuits. The electrical characteristics and models of the TSVs are very crucial in enabling the timing analysis and CAD in 3D integrated circuits. In this paper, an analytical model for the propagation delay of the TSV as a function of its physical dimensions is proposed. The presented analytical model is in great agreement with simulations using electromagnetic field solver and lossy distributed- line circuit model. Compared to earlier interconnect delay models, the presented analytical model provides higher accuracy and fidelity in addition to its simplicity. Hence, the presented analytical model is very useful in the analysis of 3D integrated circuits.