Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits

Uthman Alsaiari and Resve Saleh
The University of British Columbia


As the number of transistors on a chip begins to exceed 1 billion and their sensitivity to defects begins to degrade overall yield, it will be mandatory to assign a portion of the transistors for the purposes of Built-in-Self-Test (BIST) and Built-in-Self-Repair (BISR) as part of the supporting circuitry. Here, we focus on the self-test and self-repair of flip-flops (FFs), and their associated interconnect, using spare FFs to replace faulty ones. We describe our method to determine the number of spares based on delay and yield analysis. Using these results, we partition the flip-flops in a sequential design to improve the yield while keeping the delay and area overhead low. Although we apply this redundancy approach only to non-critical paths in the circuit so that no timing penalty is incurred, we find that it can still provide significant improvement in the overall yield. A number of sequential benchmark circuits from ITC99 are compared with and without redundant flip-flops, and also with and without partitioning. The total area overhead of our method is 8% on average while improving the yield by 6-29% and incurring no timing penalty.