A Statistic-based Approach to Testability Analysis

Chuang-Chi Chiou,  Chun-Yao Wang,  Yung-Chih Chen
National Tsing Hua University


This paper presents a statistic-based approach for evaluating the testability of nodes in combinational circuits. This testability measurement is obtained via Monte Carlo simulation governed by the formulated Monte Carlo model. The Monte Carlo simulation is terminated when the predefined error with respect to the Monte Carlo model, under a specified confidence level, is achieved. We conduct the experiments on a set of ISCAS’85 and MCNC benchmarks. As compared with previous work, our approach more efficiently evaluates the testability with less error rate. Additionally, we apply our approach to improve the ATPG program in SIS. The experimental results show that the improved ATPG program finds the test pattern with 14% CPU time reduction on average.