Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution

Shinya Abe,  Masanori Hashimoto,  Takao Onoye
Osaka University


Influence of manufacturing variability on circuit performance has been increasing because of finer manufacturing process of semiconductor and lowered supply voltage. In this paper, we focus on mesh-style clock distribution which is believed to be effective for reducing clock skew, and we evaluate clock skew considering manufacturing and design variability. Considering MOS transistor variation - random and spatial correlation variation

- and non-uniform flip-flop (FF) placement, we demonstrate that spatially-correlated variation and severe non-uniform FF distribution can be major sources of clock skew. We also examine the dependency of clock skew on design parameters, and reveal that finer clock mesh does not necessarily reduce clock skew.