Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-threshold Operation

Joseph Ryan and Benton Calhoun
University of Virginia


This paper examines latch style voltage mode sense amplifiers for operation in the sub-threshold region, where VDD<VT. We show that the offset gets worse relative to strong inversion as technology scales. Furthermore, increasing the sizes of devices in the sense amplifier does not yield the reduction of input referred offset according to 1/(WL)^0.5 that is achieved for strong inversion operation. We analyze the source of the offset and propose circuit level operating principles for minimizing its impact in sub-threshold SAs. This design methodology will optimize sub-VT SAs for more robust ultra low power operation.