Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses

Krishnan Sundaresan1 and Nihar Mahapatra2
1Sun Microsystems, Inc., 2Michigan State University


Power dissipation in long interconnects and increasing wire temperatures due to (self) Joule heating are becoming important issues to address in nanometer-scale technologies. While many low-power bus encoding schemes have been proposed, no encoding techniques exist for explicitly reducing temperatures in high-speed on-chip signal buses. In this work, we propose: (1) an interconnect/wire signaling and layout optimization that considers self and inter-wire coupling activities and is tailored to data traffic characteristics; (2) an integer linear programming (ILP) technique to optimize bus energy and; (3) a novel methodology to add thermal constraints to this ILP optimization to reduce not only average but also peak wire temperatures. Our contributions enable a designer to efficiently explore the hottest wire temperature and total bus dynamic energy trade-off space. One such trade-off point yielded a thermally-constrained, energy-optimal encoding scheme that reduced wire temperatures by up to 12.26 degC (12.96 degC) for data (instruction) bus and significant average energy savings of 14.24% (16.17%) for data (instruction) bus. These results are still much better than energy reductions obtained by previous work.