Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach

Daniel A. Andersson1,  Lars 'J' Svensson2,  Per Larsson-Edefors2
1Department of Computer Science and Engineering, Chalmers, 2


We analyze the correlation between different parameters of the on-chip power distribution grid and their impact on noise. By using factor analysis we are able to uncover correlations between power grid design variables and power supply noise. From our analysis of 300 different grids in a 65-nm process, we derive the correlation and impact that a change in power grid design variables will have on noise. The results from this analysis can be used as guidelines when designing a robust power distribution grid.