Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability

Aseem Gupta1,  Fadi Kurdahi1,  Nikil Dutt1,  Kamal Khouri2,  Magdy Abadir2
1University of California Irvine, 2Freescale Seminconductor


In this paper we propose thermal aware global routing of interconnects which reduces the probability of failure of chips due to interconnect failures. Temperature has a very serious effect on the Mean Time to Failure (MTF) of interconnects because of electromigration. We present TAGORE, a Thermal Aware Global Router. TAGORE achieves a reduction in the probability of failure by routing more wires in the colder regions of the chip and less wires in the hotter regions of the chip. We observed that TAGORE reduced the number of wires in the hottest region of a chip by up to 19.95% and by an average of 12.29%. This resulted in a decrease in the failure rate by up to 292 failures per million hours of operation. We also perform an analytical examination of the reduction in the probability of interconnect failure and the failure rate. The analysis shows that there is a reduction in the probability of failure of a chip if fewer wires are routed in the hot regions. This approach to reliability improvement does not require any addition of redundant wires or vias.