Process Variation Aware Bus-coding scheme for Delay Minimization in VLSI Interconnects

Raghunandan Chittarsu,  Sainarayanan K S,  Srinivas M B
IIIT Hyderabad


Process variations can have a significant impact on both device and interconnect performance in Deep Sub-Micron (DSM) technology. In this paper, initially authors discuss the effects of process variations on bus-encoding schemes for delay minimization in VLSI interconnects. Later, process variation aware bus-coding scheme is proposed to reduce delay in interconnects. It is shown that if process variability is taken into consideration, effective capacitance of the bus lines varies because of which the amount of delay that each crosstalk class causes is going to vary. SPICE simulations are carried out for interconnect lines of different dimensions at various technology nodes (180, 130, 90 and 65 nm) to find out variation of the effective capacitance on bus lines. Further, simulation results have shown that variation-aware coding scheme achieves an effective delay reduction (after considering delay overhead of encoder and decoder blocks) of about 36.41% on an average.