This paper addresses the problem of optimizing metallization patterns of back-end connections for the DMOS based driver since the back-end connections trend to dominate the overall on-resistance Ron. we propose a heuristic algorithm to seek for better shapes for the metallization patterns targeting at minimizing Ron and balancing the current distribution. The algorithm initially relaxes the concerned patterns with allowing overlap and then repeatedly remove the overlap subject to the geometric constraint and the current density constraint. In order to speed up the analysis, the resistance network is modified by inserting ideal switches to keep the conductance matrix constant. Simulation on two drivers from industrial TEG data demonstrates that our algorithm can reduce Ron effectively by shaping metals appropriately within a given routing area.